1. The Four Via Types in RF PCBs: Distinct Roles

RF PCBs use four via classes with distinct SI functions. Through‑hole vias (PTH) are the traditional full‑board structure, but their length and stub effect drive up parasitic inductance in high‑frequency applications. Blind and buried vias constrain layer‑to‑layer connections to only the necessary span, shortening transmission length and cutting reflection. Stitching vias don't carry signal — they surround RF traces to provide return‑current paths and act as EMI walls.

Practical rule: signal vias should be shortest, straightest, lowest‑parasitic; ground vias should be evenly distributed, tightly hugging signal vias, sufficient in count; stitching vias should be spaced according to wavelength and band. These three roles cannot be conflated — routing too many through signal vias, or spacing ground vias too sparsely, are classic starting points for RF layout mistakes.

2. Frequency Bands Are the Watershed: <3 GHz, 3–5 GHz, >5 GHz, >90 GHz

The first engineering judgment in RF via design isn't “which via type” but “which frequency band.” The band determines via impedance behaviour, whether stitching vias are needed, whether antipads must shrink, and whether waveguide alternatives should replace through‑vias.

| Band | Key Considerations | Design Countermeasures | | :--- | :--- | :--- | | < 3 GHz | Via impedance is close to trace impedance; return‑path is the main concern | Ground vias adjacent to signal vias for 50 Ω transition; antipad ≥ landing pad; stitching vias usually optional | | 3–5 GHz | Via impedance mismatch begins influencing SI | Include via section in impedance calc; introduce stitching vias as needed | | > 5 GHz | Via becomes inductive; impedance can rise 3–4× characteristic impedance | Add stitching vias, shrink antipad, tune for flat input impedance up to 40–50 GHz; avoid over‑close via/antipad spacing (excess capacitance) | | > 90 GHz | Standard via transitions insufficient | Move to coplanar waveguide, aperture coupling, or stepped blind/buried via approaches |

Practically, above 3 GHz the via must be included in full 3D EM simulation; 2D‑only impedance analysis will substantially under‑report mismatch above 5 GHz.

3. Challenge 1: Parasitics — Proximity Beats Size

Via parasitics are the primary source of GHz‑band signal degradation. A common intuition is that “bigger via = lower inductance” — but that's not how the physics works. Rick Hartley illustrated this with concrete measurement: on a 62 mil board, two 10‑mil‑drill / 20‑mil‑pad vias spaced 250 mil apart form a loop with roughly 2.5 nH inductance; doubling via diameter drops that only to 2 nH — a 20% improvement that isn't worth the routing‑density cost. But moving the same two vias to 8–12 mil apart drops inductance to 1 nH — a 50% reduction.

“Inductance is a proximity effect, not a size effect.”

That single insight rewrites via design priority:

• Signal via diameters should land in the 8–16 mil (0.2–0.4 mm) range, with related ground vias hugged as close as possible.
• The smaller the loop area between signal and ground via, the lower the parasitic inductance.
• Power vias should be arranged in alternating power–ground pairs to avoid the solenoid effect that same‑type via clusters produce.

4. Challenge 2: Antipad Sizing Controls Via Impedance

The antipad — the reference‑plane cutout around the via — looks like a fabrication detail but is actually the most direct engineering lever for controlling via impedance. Holding drill diameter constant and adjusting antipad diameter alone can shift via impedance from ~30 Ω to over 60 Ω, at essentially zero cost.

For a 62 mil board with a 10 mil drill, antipad radius vs via impedance runs roughly:

| Antipad radius (mm) | Via impedance (Ω) | | :--- | :--- | | 0.4 | 36.7 | | 0.5 | 44.5 | | 0.6 | 50.0 | | 0.65 | 52.3 | | 0.8 | 57.7 | | 1.0 | 63.0 |

Theoretical best return loss lands near antipad radius 0.6–0.65 mm (diameter ~1.2–1.3 mm) , giving near‑50 Ω via impedance.

Practical notes: antipad can't be too small (excess capacitance pulls impedance below target) or too large (mechanical strength and reference‑plane continuity suffer); differential‑signal via diameters must be matched to avoid skew; complex stack‑ups need a 3D solver to model return paths correctly — don't rely on simplified 2D formulas.

5. Challenge 3: Ground Via Layout Drives EMI and Isolation

Ground vias are the most‑discussed yet most‑often‑mishandled part of RF design. Core principle: the closer ground vias sit to signal vias, and the closer their spacing approaches λ/20, the shorter the return path, the lower the EMI, and the better the isolation.

At common frequencies:

• 2.5 GHz → λ/20 ≈ 6 mm
• 5 GHz → λ/20 ≈ 3 mm
• 25 GHz → λ/20 ≈ 0.6 mm

mmWave via‑fence density gets very high.

Common pitfalls:

1. Don't daisy‑chain ground connections — series inductance accumulates and degrades high‑frequency return.
2. Each shunt component (e.g., decoupling capacitor) should get at least two ground vias; a via ground island is even better.
3. The QFN central thermal pad must be populated with ground vias serving both electrical ground and thermal path.
4. Via fences flanking microstrip traces need a top‑side metal strap (no GND plane on top), while stripline fences must ground through both top and bottom planes.

Small details individually, but cumulatively they determine board‑level EMC performance.

6. Challenge 4: The Via Is Also a Thermal Path

In high‑power RF designs, vias carry heat as well as signal — especially under exposed pads of PAs, high‑current driver ICs, and automotive radar chipsets, where thermal transfer relies almost entirely on the thermal via array beneath the package conducting into inner‑layer copper or the bottom heatsink.

Frequently under‑appreciated thermal options:

1. Thermal via density matters more than individual via size — many small vias beat few large ones for building an effective thermal path.
2. In thermally critical designs, PTH plating can be thickened from the standard 25 μm to 100 μm to improve vertical conduction.
3. Copper‑filled vias outperform silver‑epoxy paste (typical 4–30 W/mK for the paste vs 400 W/mK for solid copper).
4. Blind vias under 0.2 mm diameter and 0.3 mm depth can be fully plated with copper via blind‑hole plating.
5. In‑board copper coins are the most effective structure under high‑power RF amplifiers and must be discussed with the fabricator during design planning.

Closing: The Via Is RF's Most Underestimated Failure Mode

Looking at GHz‑band RF designs, cases where “layout passed review but failed high‑frequency measurement” trace back to the via about eight times out of ten — parasitic inductance, antipad sizing, ground via layout, or thermal path. Via design isn't about a single parameter but about consistency across band → dimensions → spacing → grounding → thermal; a single link out of tune with the frequency band will fail in the least expected place.

eCloud provides RF/microwave PCB, mmWave board, high‑frequency/high‑speed (Rogers, Megtron 6/7, TLY, PTFE), and mixed‑dielectric stack‑up prototyping and production, with support for back drilling, via‑in‑pad, and copper‑filled microvia processes. Have an RF or mmWave project entering planning? Talk to our engineering team at the Taoyuan service window for an in‑person via and stack‑up DFM review — align impedance, antipads, stitching‑via spacing, and thermal path before layout release, and drive EMC and yield risk down at the design stage.