1. The Physics of EMI and EMC: Fields, Loops, and Frequency Bands

EMI is, at its core, electromagnetic energy leaking from one circuit to another. There are two leakage paths: radiation through the air (radiated emission) or conduction through cables (conducted emission). External noise enters the system through the same two paths. EMI is most problematic between 9 kHz and 6 GHz – above that, interference typically stays within a single board and falls into the signal integrity (SI) category instead. EMC (electromagnetic compatibility) is the flip side: in a regulated environment, the board must neither emit excessive noise nor be susceptible to external interference. Common EMI sources are summarised below:

| Type | Source | Mechanism | | :--- | :--- | :--- | | High‑speed switching | Digital clocks, SMPS, DC‑DC, PWM | Fast rise/fall edges produce high‑frequency harmonics | | Cable radiation | Unshielded cables, ribbon cables | Length approaches λ/4, becomes a resonant antenna | | Trace radiation | Long, unterminated high‑speed traces | Trace itself becomes a radiating antenna | | Plane defects | Split grounds, enclosure seams | Slot approaches λ/2, becomes a slot antenna | | Floating conductors | Unterminated IC pins, test pads, heatsinks | Any floating metal acts as an antenna | | Insufficient decoupling | Missing or misplaced decoupling caps | High‑frequency noise reaches the power rail |

The common pattern is clear: any “rapidly changing current or voltage” combined with an “uncontrolled loop” will radiate. All 7 principles below are about solving these two things.

2. Principle 1: Stackup Decides Everything – 6 Layers Is the EMC Baseline

Stackup is the first watershed for EMC. Every signal layer must have an adjacent solid reference plane (ground or power) – this is the most non‑negotiable rule.

• 6‑layer boards: L1 signal / L2 GND / L3 signal / L4 signal / L5 PWR / L6 signal (or similar) ensures every signal layer has an adjacent reference plane
• 4‑layer boards: L1 signal / L2 GND / L3 PWR / L4 signal is the minimum acceptable arrangement; L4 still lacks an adjacent reference plane and remains an EMI weak point
• Outer‑layer copper pours: if used, they must be heavily stitched to internal GND with stitching vias; otherwise a floating pour becomes an antenna
• Single‑sided or no‑reference layers: return paths must be drawn manually, with guard traces added where needed

Many EMC failures trace back to 2‑ or 4‑layer boards being pushed into high‑speed designs without adjacent reference planes for every signal. Stackup decisions have far greater impact than adding shield cans later.

3. Principle 2: Transmission Line Structure and Ground Integrity

Choosing the right transmission line structure is the second gate to keeping traces from becoming antennas.

• Microstrip: surface trace over an internal reference plane. Suitable for most digital, I/O, and power routing – easy to implement and debug
• Stripline: signal sandwiched between two reference planes. Best for clocks and sensitive analog signals – fields are fully contained between the planes
• Don't split ground planes: many engineers split GND to “isolate digital and analog,” but this forces return currents to detour, increases loop area, and worsens EMI. The correct approach is a single continuous GND, with isolation achieved through routing zones and component placement
• Guard traces: ground traces flanking sensitive signals, stitched to GND via multiple vias, suppress field spreading

For 224G PAM4 and PCIe 6.0 designs, stripline paired with HVLP copper foil and M8/M9‑grade CCL has become the default – precisely because of stripline's superior field containment over microstrip.

4. Principle 3: Return Paths and Minimum Loop Area

Every signal forms a loop with its return path on the reference plane – and the larger the loop, the stronger the radiation. Controlling loop area is the lowest‑cost, highest‑leverage decision in EMC design.

• Keep traces at least one dielectric thickness from the board edge (the 20H rule is more conservative)
• Shorten critical signals (clocks, PWM, high‑speed differential pairs); shorter physical antennas radiate less
• Use differential pairs with symmetric returns instead of single‑ended signalling to reduce common‑mode emissions significantly
• Avoid high‑speed signals crossing ground splits; if unavoidable, place stitching vias or 0 Ω jumpers at the crossing

The most common violation in practice is “letting the clock trace meander across the board for layout aesthetics.” An extra 1 cm of trace seems harmless, but at 1 GHz harmonics (λ ≈ 30 cm in air), doubling loop area can raise radiated emissions by 6 dB.

5. Principle 4: Stitching Vias and Via Fences at Layer Transitions

When a signal changes layers through a via, the return path is broken – unless explicitly bridged.

• Stitching vias at transitions: when a signal moves from L1 to L4, the return current must “jump” from L2 GND to the GND near L4 (e.g., L5). Place 1–2 ground vias next to the signal via to give the return current a path
• No stitching needed under a single reference: if L1 → L3 both reference L2 GND, the via passes through continuous GND and the return path is naturally continuous
• Via fences along board edges: a perimeter ring of ground vias creates a vertical Faraday cage that contains high‑frequency fields within the board
• Spacing must be < λ/20: in FR‑4 at 1 GHz, effective wavelength λ ≈ 18 cm, so λ/20 ≈ 9 mm – meaning via fence spacing should be under 9 mm. To protect against 5 GHz harmonics, spacing tightens to roughly 1.8 mm

The blind spot here is treating stitching vias as decoration. Without calculating spacing based on frequency and the actual transition geometry, the effect is limited.

6. Principles 5–7: Filtering, Shielding, and Eliminating Floating Conductors – Three Edge Controls

Once stackup, loops, and return paths are sorted, the final line of defence is edge control – managing energy entering and leaving the board.

• Decoupling capacitors: placed millimetres from the IC's power/GND pins. The smaller the IC → cap → GND loop, the better noise is suppressed at the source. Connection to the GND plane must be direct and low‑inductance
• EMI filters: filter every power input, I/O connector, and communication port before cables leave the board. Unfiltered cables become antennas. Passive LC, π, or C filters are sufficient for most digital/embedded designs
• PCB‑level shield cans: place shields over oscillators, SMPS, RF receivers, and precision analog blocks. Shield grounding must use multiple low‑impedance contacts; otherwise the shield itself becomes an antenna
• Enclosure shielding: when a metal enclosure acts as a Faraday cage, every cable through the enclosure must be shielded or filtered at the entry point; the largest shield gap dimension must be < λ/20
• Eliminate floating conductors: terminate unused IC pins per datasheet, remove leftover test traces, and tie every copper pour, heatsink, and metal bracket to a defined GND reference

Order matters – filtering handles conduction, shielding handles radiation, and they typically work together. Jumping to shielding before fixing stackup and loops is like patching a leak after the water has flooded the room: expensive and only partially effective.

Closing: EMC Is Calculated at Layout, Not Patched Before Test

Boards that fail EMC usually fail because of stackup and routing decisions, not because they were “under‑shielded.” A 4‑layer board running a 1 GHz clock with an unplanned return path and floating outer copper pour cannot be saved by any amount of ferrite beads, shield cans, or absorbers added later. FCC Part 15, CISPR 11, and MIL‑STD‑461 define test thresholds – they are not design guides. What actually gets a board through certification on the first attempt is calculating fields, loops, and frequency bands at the design stage.

In our DFM reviews, three EMC risks come up most often:

• 4‑layer boards used for high‑speed designs where L4 has no adjacent reference plane
• GND split to “isolate digital and analog” – actually forcing return currents to detour
• High‑speed layer transitions without stitching vias

eCloud provides integrated prototyping and production for HDI and multilayer high‑speed boards, with extensive EMC design experience across AI acceleration, high‑speed networking, automotive, and silicon photonics applications. Planning a high‑speed project? Talk to our engineering team during layout – get stackup, impedance, and EMC‑related DFM feedback early, so you don't discover at the EMC lab that the board needs to be re‑laid out.