1. What a Stack‑up Actually Defines

A stack‑up is the complete top‑to‑bottom specification of a multilayer board. At minimum it must define four things: layer assignment (Signal / Power / GND), copper weight per layer (1/2 oz, 1 oz, 2 oz, etc.), dielectric thickness between layers (both core and prepreg), and target impedance for controlled traces (e.g., 50 Ω single‑ended, 100 Ω differential). Together these four parameters lock in trace characteristic impedance, inter‑layer coupling, and final board thickness.

The conventional standard board thickness is 62 mil (1.57 mm), but 93 mil (2.36 mm) and 125 mil (3.17 mm) have become the second and third industry defaults for high‑layer‑count, high‑current, or high‑thermal‑mass applications. A complete stack‑up should be aligned with the fabricator before design release – so you don't discover mid‑fab that the available prepreg mix can't hit the target impedance, or that the layer count exceeds the fabricator's press limits.

2. Copper Foil, Prepreg, and CCL: The Three Building Blocks

A multilayer board is physically a stack of copper foil, prepreg, and copper‑clad laminate (CCL).

Copper Foil

Copper foil is graded by roughness – HTE, RTF, VLP, HVLP – with tooth height dropping from 3–5 μm on standard grades down to sub‑0.5 μm on HVLP4/5. Above ~25 GHz operating frequency, surface roughness loss (skin‑effect loss) can exceed dielectric loss, and picking the right foil often matters more than picking the right resin.

Prepreg

Prepreg is a semi‑cured epoxy‑impregnated glass cloth that melts and bonds the layers during lamination; the choice of glass style (1078, 2116, 3313, 1067) sets the sheet thickness and effective Dk.

CCL (Core)

CCL is prepreg fully cured with copper foil on both sides – the substrate on which inner‑layer circuitry is etched. Common Taiwan R&D choices range from entry‑level FR‑4 High‑Tg, through mid‑tier IT‑180A / TU‑863+, up to high‑speed Megtron 6/7, RO4350B, and TU‑933+ – each choice directly locking in Df, Dk, and moisture absorption.

3. Power and Ground Planes: The Hidden Backbone of SI and EMI

In a multilayer board, power and ground planes are not there just to carry supply current – their core job is to provide a low‑impedance return path for high‑speed signals. A high‑speed trace running over a continuous reference plane behaves as a predictable transmission line; the moment that reference is split, punched by a via, or crossed by the signal, the return current must detour, and both EMI radiation and crosstalk rise immediately.

Three practical rules:

1. High‑speed signal layers must sit adjacent to a continuous GND reference, and traces should not cross reference‑plane splits.
2. Tight coupling between power and ground planes forms an intrinsic high‑frequency decoupling capacitor, particularly effective at suppressing GHz‑band PDN noise.
3. Power‑island partitions should avoid running directly beneath high‑speed traces to prevent return‑path gaps.

All three are stack‑up decisions – discovering a broken reference plane after layout is usually unfixable.

4. One‑Shot vs. Sequential Lamination: The Complexity Watershed

The multilayer manufacturing flow condenses to: inner‑layer etch → AOI → oxide → lay‑up → vacuum lamination → drilling → desmear → electroless copper → plating → outer‑layer processing. A design that presses everything in one pass is called “one‑shot lamination” and is the most economical route. When the design requires buried vias, blind vias, or advanced HDI structures, it enters “sequential lamination” – inner sub‑cores are pressed, drilled, plated, and filled first, then each successive pair of layers is added, repeated 2–4 times.

Each additional sequential stage extends process time, compounds material CTE mismatch, tightens registration tolerance, and drops yield. Using a 4‑layer one‑shot design as baseline:

| Lamination Grade | Sequential Passes | Yield Impact (vs 4L one‑shot) | Typical Use | | :--- | :--- | :--- | :--- | | One‑shot | 0 | Baseline | Standard 4–12L boards | | 1+N+1 | 1 | –5% to –10% | 0.5–0.65 mm pitch BGA | | 2+N+2 | 2 | –15% to –25% | 0.4 mm pitch BGA, complex HDI | | 3+N+3 | 3 | High‑risk band | Mobile SiP, ultra‑dense modules |

This “sequential‑lamination cost curve” is the single most under‑budgeted item in multilayer BOM cost.

5. HDI Nomenclature: What X+N+X Actually Tells the Engineer

HDI stack‑ups use the X–N–X convention:

• X is the number of microvia stages per side
• N is the number of core layers between them

For example:

• 1+4+1 is a 6‑layer board with 4 inner cores and one laser blind via stage on each side
• 2+4(6b)+2 is an 8‑layer stack with 4 inner cores plus 6 buried‑via layers, and two microvia stages per side

Higher X means more sequential‑lamination passes and higher achievable routing density.

Practical mapping:

• 0.65 mm pitch BGA → typically fans out safely with 1+N+1
• 0.5 mm pitch BGA → commonly needs 1+N+1 or 2+N+2
• 0.4 mm pitch BGA → almost always requires 2+N+2 or higher, often with via‑in‑pad and copper‑filled microvias

If the designer works the logic backward from the start – component pitch → microvia stages needed → sequential lam passes → stack‑up grade – it's often possible to drop from 2+N+2 back to 1+N+1 without hurting layout, cutting fabrication cost substantially.

6. Five Practical Recommendations for Stack‑up Design

1. Plan layer count and board thickness together. Estimate signal / power / GND allocation and board‑thickness ceiling before starting layout; adding layers mid‑project disrupts impedance calculations.
2. Cap sequential lamination at three passes. Each additional stage raises time, cost, and yield risk non‑linearly. Prefer staggered vias over stacked vias when possible.
3. Explicitly document buried and blind via ranges. On the fab drawing, mark buried via layer spans, whether blind vias need copper fill, and whether vias are stacked or staggered – this cuts EQ rounds substantially.
4. Confirm materials are compatible with sequential lamination. Some high‑speed resin systems degrade under repeated high‑temperature press cycles; Tg, CTE, and lamination‑cycle limits should be reviewed with the fabricator.
5. Run a stack‑up trial before layout. Back‑solve trace width from target impedance, snap dielectric thickness to standard prepreg glass styles, and confirm the board‑thickness ceiling. One day here saves two weeks later.

Closing: Stack‑up Is Design, Not Just Fabrication

A well‑planned stack‑up solves signal integrity, EMI, board thickness, yield, and cost in one document; a rushed stack‑up tends to bite back in the most expensive way – at EMC compliance, DDR training, or SerDes impedance test. A multilayer stack‑up is really a contract between design and manufacturing, and the earlier that contract is signed, the smaller the engineering risk.

eCloud specialises in multilayer, HDI blind/buried via (1–4 stage sequential lamination), high‑frequency/high‑speed (Rogers, Megtron 6/7, TLY, PTFE), and mixed‑dielectric stack‑up prototyping and production. Have a multilayer or HDI project entering the planning phase? Talk to our engineering team at the Taoyuan service window for an in‑person stack‑up and DFM review – get impedance, board thickness, material, and lamination grade aligned before layout release, and drive cost and yield risk down at the design stage.