Advanced Manufacturing Series: High-Density Interconnect (HDI) Blind and Buried Vias Process Limits and Design Pitfall Guide

HDI Design Blind Spots: Stacked Vias, Aspect Ratio, Resin Filling, and Via‑in‑Pad Traps

Blind Spot #1: Did you choose “Stacked Vias” or “Staggered Vias”? (Huge Cost Difference)

This is the key most frequently overlooked by many engineers. When you need to connect two or more consecutive layers of blind vias, there are two routing methods:

• Staggered Vias (Stepped Drilling): After the first stage blind via is drilled, you shift a slight distance to drill the second stage blind via. This manufacturing process is mature and only requires standard resin filling. It features lower costs and high yield rates.
• Stacked Vias (Coaxial Continuous Drilling): The second stage blind via is stacked directly on top of the first stage blind via. To provide a solid base for the upper laser via, the underlying blind via must use an extremely expensive “copper plating filling” process to fill it completely with pure copper. Not only does this double the plating time, but if any chemical residue or bubbles remain in the hole, it will burst when passing through the high‑temperature reflow oven (commonly known as board bursting/delamination). Unless absolutely necessary, please prioritise staggered via designs.

Blind Spot #2: The Physical Limits of Laser Blind Via “Aspect Ratio”

The “0.8:1” frequently mentioned refers to the aspect ratio of laser drilling (the ratio of dielectric layer thickness to blind via diameter). A laser beam is like an inverted cone; if the insulation layer is too thick and the via diameter too small, the laser cannot successfully penetrate to the bottom copper foil, or it results in a bottom diameter so small that the subsequent plating solution cannot enter at all, causing a void in the via wall copper.

• Design Iron Rule: The dielectric layer thickness must absolutely not exceed 0.12 mm. It is recommended to pair a thin prepreg (PP) of about 0.076 mm with a 0.1 mm diameter laser blind via. This is currently the golden ratio for the most stable yield.

Blind Spot #3: The Math of Hole‑Filling Processes – Is There Enough Resin?

Once blind and buried vias are drilled, cavities are inevitably left inside. These cavities must be filled, otherwise the board material will collapse during lamination. Fabrication houses typically use two filling methods:

1. Prepreg Lamination Filling (The Cost‑Saving Method): Directly utilising the high‑temperature melted prepreg resin during lamination to squeeze into the blind/buried vias.

   • Hidden Danger: The amount of resin in the prepreg is fixed. If your inner layer routing is heavily etched away (extremely low residual copper rate), and there are thousands of blind vias on the board, the resin will be instantly absorbed. Once there isn’t enough resin to fill all the gaps, microscopic bubbles will be left between the layers, which is the root cause of future delamination due to thermal expansion and contraction.

2. Resin Plugging (The “Pay to Avoid Disaster” Method): When the board thickness is greater than 0.4 mm, or the buried via diameter is greater than 0.2 mm, the prepreg resin is absolutely insufficient. At this time, an independent process must be added before lamination. Using a dedicated screen, polymer resin is forcibly squeezed into each buried via, baked dry, and ground flat before lamination.

• Design Recommendation: Engineers do not need to personally calculate the resin volume, but before releasing the design to manufacturing, as long as your design includes large copper‑free areas and dense buried vias, be sure to proactively confirm with the fabrication house: “Is the current prepreg resin content sufficient? Do we need to add an extra resin plugging process?”

Blind Spot #4: The Stacking Effect of Via‑in‑Pad and Ultra‑Thin Cores

• The Price of Via‑in‑Pad: To save space, vias are drilled directly onto the surface component’s solder pads. This means the factory must fill the hole with resin and then plate a flat layer of copper over the surface. This will increase the overall manufacturing difficulty by more than 15%.
• The Plating Thickening Trap: When your inner layer design requires 2 oz heavy copper and includes plated blind/buried vias, the factory usually takes a 1 oz core board and plates both the via walls and the surface up to 2 oz. During this process, the entire board essentially thickens by 1 oz. If the mechanical engineer does not account for this “plating increment”, the final product is highly likely to exceed the chassis assembly tolerances.

Conclusion

High‑Density Interconnect technology leaves no room for error, and various process limits cannot be arbitrarily combined. Before finalising the routing layout, strictly executing a Design for Manufacturing (DFM) review and clarifying stacked via requirements, aspect ratio limits, and resin filling risks early on is the only golden rule to ensure the product can smoothly enter mass production on schedule and within budget.