Deep Dive into High-Frequency and High-Speed Server PCB Manufacturing Technology in the Era of AI Computing Power

22‑Layer Server Motherboard Process Technology & Optimization Guide

01 | Technical Difficulties and First Article (FA) Bottlenecks

1. Key Factors Influencing Impedance and Loss

Material Characteristics: High‑end server substrates are classified into five grades based on their Df values. For this project, the client specified Panasonic’s low‑loss material R‑5775(G) (Megtron 6 grade, Dk: 3.46, Df: 0.005). Its Tg, Td, and Coefficient of Thermal Expansion (CTE) required strict evaluation.
Circuit Technology: Conductor loss depends on trace width uniformity and copper foil roughness. Reverse Treated Foil (RTF) was selected for this project, and SI Coupons (insertion loss validation modules) of varying lengths (2/5/10 inches) were designed for functional verification.
Depth‑Controlled Backdrilling: The remaining depth of the stub directly dictates the quality of the signal insertion loss, making it the core technology for meeting impedance and loss targets.

2. First Article (FA) Trial Production Pain Points

The 22‑layer server motherboard developed for this project has a finished board thickness of 2.95 mm ± 10%. The inner layers consist of 1/1 oz and 2/2 oz core boards, with a design trace width of 3.5 mil and an aspect ratio reaching 14.75:1. It also utilises a Plated Over Filled Via (POFV) process. Trial Anomaly: After manufacturing through the traditional workflow, the insertion loss significantly exceeded the standard, and the hole copper thickness was excessively thick, failing to meet the strict SI standards.

02 | Technological Innovation and Process Optimization (DOE)

1. DOE Experimental Results for Insertion Loss Optimization

The process engineering team established a four‑factor, two‑level full factorial Design of Experiments (DOE). The key variables investigated were: trace width compensation, prepreg (PP) resin content, panel rotation angle, and brown oxide micro‑etching solution.

By measuring the loss values of the 85‑ohm transmission line at various high frequencies, the optimal process parameters (Scheme 11) were identified:

Anti‑Fiber Weave Effect: Altering the layout routing direction from the traditional 3 degrees to a 7‑degree tilt breaks the parallel overlapping phenomenon between the traces and the glass fiber bundles, reducing signal loss by 2% – 3%.
Ultra‑Low Roughness Solution: Utilising an ultra‑low roughness brown oxide solution reduces unnecessary reflections of high‑frequency currents on the copper surface, shrinking the loss value by 3% – 7%.
PP Resin Content: A resin content of 75% outperformed 70% in loss performance. It provides better dielectric uniformity at high frequencies, reducing loss by 1% – 3%.

2. Production Flow Optimization: Flipped Two‑Stage Plating

The conventional process requires three plating cycles (Panel Plating, Capping Plating, Pattern Plating), resulting in backdrilled holes with excessively thick copper and undersized diameters. The team reorganised and optimised the conventional process:

Original Flow (Traditional)
Material Cutting → Inner Layer → Lamination → Laser Blind Via → Drilling 1 (Through‑holes + depth‑control drilled at once) → Panel Plating → Pattern Plating 1 → Resin Plugging → Copper Grinding/Reduction → Capping Plating → Outer Layer → Pattern Plating 2 → Backdrilling → Etching.
New Flow (Flipped Optimisation)
Material Cutting → Inner Layer → Lamination → Laser Blind Via → Drilling 1 (Only vias requiring plugging) → Panel Plating 1 → Pattern Plating 1 → Resin Plugging → Copper Grinding/Reduction → Drilling 3 (Remaining non‑plugged through‑holes) → Panel Plating 2 → Outer Layer → Pattern Plating 2 → Final Backdrilling → Etching.

Improvement Benefits: The drilling process was decoupled into a two‑stage operation. The plugged holes and Capping plating were handled first, and standard signal through‑holes were drilled in the second stage. This successfully prevented all backdrilled holes from undergoing three repetitive copper platings, completely resolving the pain points of copper over‑thickness and backdrill diameter shrinkage.

03 | Core Manufacturing Points for a 22‑Layer Server Motherboard

Material Cutting & Inner Layer
After cutting, a 190 ℃ × 4 hour mandatory bake is performed to release stress. Inner layers utilise high‑precision LDI exposure, with trace width/spacing at 3.5 / 4.0 mil, and impedance trace width tolerance strictly controlled within ±8%. The AOI fine‑line inspection function is enabled, and trace patching is strictly prohibited.
High‑End Lamination
Seven registration pins are used to closely monitor layer shift. A low‑roughness brown oxide line is selected. Lamination uses a dedicated high‑end profile with the vacuum extraction time extended by 5 minutes to ensure 100% saturated resin filling. Dielectric thickness tolerance is controlled within ±10%.
First‑Stage Drilling & Plating
Drill 1 only targets holes requiring resin plugging. Drill bits for hole diameters < 0.5 mm are set for mandatory replacement after 500 hits (CPK > 1.33). After Plasma desmear, the boards enter a pulse plating line to ensure initial hole copper reaches 0.9 – 1.0 mil.
Resin Plugging & Copper Grinding
San‑Ei 10HF resin from Japan is used for double‑sided plugging, achieving 100% fullness. Grinding maintains surface copper at 1.2 – 1.5 mil, followed by a dedicated micro‑etching line to evenly reduce base surface copper to 0.9 ± 0.1 mil.
Second‑Stage Drilling & Final Pattern Plating
A CCD drill machine creates the remaining standard through‑holes (hole position tolerance ±0.05 mm). The second round of panel and pattern plating is performed. Final finished requirements: surface copper Min 1.9 mil, hole copper Min 0.8 mil, and Capping plating dimple over plugged holes < 25 µm.
Post‑Process Control
Final backdrilling is executed (Stub strictly controlled at 7 ± 5 mil), followed by a 2.5 kg/cm² high‑pressure wash. Electroless Nickel Immersion Gold (ENIG) requires a gold thickness of 2 – 10 µ" / nickel thickness Min 118 µ", with nickel corrosion strictly controlled at < 20% to prevent black pad defects.

04 | Mass Production SI Testing Data and Yield Summary

1. Impedance and High‑Frequency Insertion Loss (Loss) Measured Data

Through integrated process optimisation in this project, all SI performance indicators were perfectly met:

Impedance Control: The 85 Ω and 100 Ω transmission lines on inner layers yielded measured values between 83.8 – 102.5 Ω, all passing inspection.
Insertion Loss (Delta‑L test method, 10‑inch transmission line) :

| Testing Frequency (GHz) | Inner Layer Measured Loss (dB/inch) | Outer Layer Measured Loss (dB/inch) | Industry Standard Upper Limit (dB/inch) | SI Comprehensive Assessment | | :--- | :--- | :--- | :--- | :--- | | 4.0 GHz | 0.286 | 0.312 | 0.350 | Passed (Excellent) | | 8.0 GHz | 0.495 | 0.534 | 0.600 | Passed (Excellent) | | 12.89 GHz | 0.721 | 0.785 | 0.850 | Passed (Excellent) | | 16.0 GHz | 0.884 | 0.942 | 1.050 | Passed (Excellent) |

2. Key Process First Pass Yield (FPY)

The overall FPY for the initial release of the high‑layer‑count (>10L) trial boards reached over 85%:

Inner Layer Circuit Yield: 91% (primary defect: ultra‑thin core boards are prone to localised folding when passing through horizontal lines).
Outer Layer Circuit Yield: 90% (primary defect: uneven copper plating at board edges leading to trace amounts of unetched residue).
E‑test and Final Inspection Yield: 86% – 88%, with finished board warpage strictly controlled at < 0.7%.

05 | Conclusion: Golden Guidelines for High‑Speed PCB Manufacturing

Prepreg Stack‑up Optimisation
High‑speed signal layers should prioritise prepregs with a high resin content (RC 75%), which can further reduce high‑frequency transmission loss by an additional 1% – 3%.
Specify Low‑Roughness Chemical Processes
Comprehensively introducing ultra‑low roughness brown oxide chemistry to replace traditional black/brown oxide can directly optimise insertion loss by 3% – 7%.
Layout Rotation Routing at 7 Degrees
Setting a 7‑degree angle between the layout routing direction and the glass fibre bundle direction (anti‑fibre weave effect) can reduce high‑frequency loss by an additional 2% – 3% compared to the traditional 3‑degree layout.
Implement a Two‑Stage Process Flow
For deep‑hole, thick boards with POFV and high‑frequency backdrilling requirements, decoupling the drilling into a “two‑stage drilling and plating” flow is the optimal manufacturing path to balance surface copper flatness and a high SI pass rate.