Chapter 1: Trace Width/Space — The Yield Cliff Between 3mil and 4mil

Why do factory sales reps often say, "4mil/4mil is standard, 3mil/3mil costs extra and has low yield"? This isn't just an equipment issue; it's a physical limitation of fluid dynamics.

1. Etch Factor & Undercut

In CAD software, lines are perfect rectangles; but in the factory's etching tank, the chemical solution attacks "omnidirectionally." As the solution corrodes the copper foil downwards, it also attacks sideways, forming a trapezoidal cross-section.

• Etch Factor Formula: F = T / X (T = Copper Thickness, X = Undercut amount).
• Practical Impact: To compensate for undercut, factories "thicken" the trace width by about 0.5~1 mil during the CAM stage.
• The Fatal Flaw of 3mil: If you design a 3mil space, and the factory compensates to maintain the trace width, the spacing becomes too small, triggering Dry Film Lock or Incomplete Etching, causing micro-shorts.

2. The Golden Ratio of Copper Thickness and Trace Width

• 0.5 oz (1/2 oz) Copper: The top choice for making 3mil (75µm) traces. Because the copper layer is thin, etching time is short, and undercut is easier to control.
• 1 oz Copper: The red line is 4mil/4mil. Forcing 3mil results in a significant drop in yield and necessitates the use of high-cost LDI (Laser Direct Imaging) equipment.
• Cost Warning: Pushing from 4mil to 3mil increases circuit density but can raise manufacturing costs by 50%~100% (requires upgraded cleanroom class and AOI inspection precision).

DfM Recommendation: Unless it is a BGA Fan-out area, try to maintain 4mil/4mil or above for the entire board. If 3mil trace width is mandatory, be sure to reduce copper thickness to 0.5 oz or 1/3 oz.

Chapter 2: Annular Ring — The Source of 90% of Scraps

The annular ring is the ultimate victim of accumulated errors in PCB manufacturing. Many RDs only look at the finished hole size but ignore the cumulative effects of "Drilling Tolerance" and "Layer-to-Layer Registration."

1. IPC Golden Calculation Formula

Don't set Pad Size by feel; apply the formula: L = a + 2b + c

• L (Min. Land Size): Minimum pad diameter.
• a (Drill Diameter): Drill bit diameter (Note: This is not the finished hole! It is usually 4-5mil larger than the finished hole for plating).
• b (Min. Annular Ring):
  • Class 2: Tangency allowed (Breakout allowed).
  • Class 3: No breakout allowed.
• c (Manufacturing Tolerance): Sum of manufacturing tolerances.

2. The Cruel Reality: How big is tolerance c?

In Taiwan's mass production factories (e.g., Unimicron, Tripod), the tolerance c for multilayer boards is at least 8~10 mil. This includes:

• Mechanical Drill Wander
• Lamination Scaling & Registration

Practical Case: If you want an 8mil finished hole (Via):

• Drill bit a = 12mil.
• If doing Class 2 (b=0), plus tolerance c=10, then Pad must be at least 22 mil.
• If you only drew an 18mil Pad, there is a high probability of "Breakout" during drilling, leading to opens or reliability risks.

Chapter 3: Teardrop — The Guardian of Yield

In high-density designs of 2025, teardrops are no longer "optional" but "standard."

1. Mechanical Stress & Breakout Protection

Teardrops increase the copper area at the junction of the trace and the pad.

• Preventing Opens: Even if the drill hole shifts (breakout), the teardrop structure ensures there is still copper connection between the trace and the hole wall, preventing electrical opens.
• Stress Dispersion: During thermal expansion and contraction (Reflow or operational heating), teardrops disperse stress, preventing the generation of Micro-cracks.

2. Myths regarding High Frequency & HDI

Many RDs worry that teardrops affect Signal Integrity (SI). In fact, modern EDA tools support "Snowman" or smooth curve teardrops, and their impedance discontinuity is far less than the risk brought by "via cracking."

Conclusion: For IPC Class 3 products or multilayer boards above 10 layers, be sure to enable the teardrop function.

Chapter 4: Taiwan Supply Chain Capacity & Yield Tiering

Taiwan's PCB industry leads the world technologically, but different manufacturers have different "Capabilities" and "Optimal Cost Points."

| Manufacturer Type | Representative Manufacturers | Technical Red Line (Mass Production Level) | DfM Strategy | | :--- | :--- | :--- | :--- | | High-End HDI / Substrate | Unimicron, Compeq | Trace Width < 2mil<br>Microvia 3mil | Suitable for AI servers, Apple-grade products. Requires mSAP process, high cost. | | Multilayer / Automotive | Tripod | Trace Width 3~4mil<br>Annular Ring Class 3 | Suitable for server motherboards, automotive radar. Focus on CAF protection and heavy copper control. | | General / Quick Turn | (Various SMEs) | Trace Width > 5mil<br>Pad > 20mil | Suitable for consumer electronics. Do not challenge limit parameters, or yield will drop below 80%. |

Chapter 5: Summary — RD's Decision Checklist

1. Don't be fooled by the Spec: A factory's Capability List saying "Min Trace Width 3mil" refers to "Limit Capability." If you want mass production without extra costs, stick to 4mil/4mil.
2. Leave margin for Annular Rings: Pad Size must be at least 12-14 mil larger than the finished hole (e.g., 8mil hole paired with 20-22mil Pad); this is the physical baseline for registration errors.
3. Turn on Teardrops: This is the most effective free method to improve yield and reliability.
4. Watch out for 1oz Copper: Running 3mil traces on 1oz copper is asking for trouble; please reduce copper thickness or widen the traces.

Mastering these red lines means you are designing not just a circuit diagram, but a product that can be manufactured with high quality.