Design Practice: Hiding Resistors and Capacitors Inside the Board — Embedded Passives Design Essentials and Manufacturing Realities

What embedded components are, and when they're worth it

Embedded components are resistors and capacitors (occasionally inductors and ICs) fabricated directly into the PCB substrate with conductive and dielectric materials rather than soldered on the surface. Versus SMT, they offer three structural advantages: space savings (surface area freed for actives and routing), no solder joints (better resistance to vibration and thermal cycling), and lower parasitics (smaller decoupling loop inductance, better signal integrity). RF performance holds up under test — an attenuator built from embedded resistors performed well up to 60 GHz, and resistive material under traces added only minor loss at 40–50 GHz.

The pragmatic rule: choose SMT when budget dominates; accept embedded's cost and process complexity only when space, reliability, thermal, or signal quality are hard requirements.

Stackup planning: dedicated inner layers and the window layer

The stackup is the first battleground. Mainstream layout tools (Altium, Allegro, CADSTAR) all support embedded components, and a few rules apply broadly:

• Allocate dedicated inner layers for embedded parts to simplify routing and reduce interference
• Keep the stackup symmetrical to prevent warpage
• Place component layers close to signal layers to minimise stubs
• Put a ground plane directly beneath the embedded layer for shielding
• Size dielectric thickness at roughly 5–10 mil for voltage safety

Resistors and capacitors differ in practice: resistors can sit directly on an existing signal layer — no window layer, no extra vias — while capacitors are best placed in a window layer near the reference plane. Thickness impact is minimal: a 10 Ω/square resistive material adds only about 1 μm, and embedded capacitance can actually reduce total thickness by letting power and ground planes sit closer together.

Impedance and high‑speed routing: one red line

Impedance continuity is where embedded designs most often go wrong on high‑speed boards. Key points:

• Account for copper thickness in impedance calculations — thicker copper lowers impedance, so trace width and spacing must be adjusted accordingly
• Never place embedded components directly beneath high‑speed traces unless they are part of the impedance‑matching network
• Converge dimensions with impedance modelling at design time and verify with TDR measurements on prototypes to locate discontinuities

Loss from the resistive layer itself is only fractions of a dB per inch — acceptable, which is why embedded resistors are widely used on PTFE‑based high‑frequency boards.

Embedded resistor selection: tolerance is the hard reality

Embedded resistance follows R = (ρ × L) / (W × T) , so value tuning is a matter of adjusting length and width — but tolerance is unavoidable: base tolerance runs about ±5%, and etching plus registration variation pushes the total to a typical 15–20%.

Three design‑side countermeasures:

1. Make electrodes slightly larger than the resistor area so the resistor stays fully within the electrode boundary
2. Keep resistor widths at 10–20 mil or above, since 5‑mil resistors show markedly higher variability
3. Confirm your fabricator uses laser direct imaging with registration held within 1 mil

Two more selection parameters: choose TCR below 100 ppm/°C for temperature stability, and after computing dissipation with P = I²R, derate power capacity by at least 25%. Thick film for high power, thin film for precision, plated resistors for high‑current and high‑frequency work.

Embedded capacitors and decoupling strategy

The biggest value of embedded capacitance is decoupling: a planar capacitor directly under an IC's power pins has far lower loop inductance than a surface SMT part. For selection:

• Set voltage ratings 20–50% above the maximum expected voltage
• Use 0.01–0.1 μF ceramic‑class values for power‑rail filtering
• Use 1–100 nF for RF filters
• Use 1–10 μF for audio applications

Layout strategy: prioritise low ESR, place capacitors adjacent to IC power pins, distribute them across multiple layers to cover a wider noise spectrum, combine embedded and discrete SMT capacitors into a complementary decoupling network, and maintain solid, continuous power planes.

Manufacturing realities: registration, drilling, and lead time

Four things to align with your fabricator before design freeze:

1. Registration error: embedded resistors use a two‑step etch, and misregistration between the two etches feeds directly into resistance value — a primary tolerance contributor.
2. Offset drilled pads from resistor areas to keep drilling heat and mechanical stress off the resistive layer; microvias can coexist with embedded parts, but clearances may need adjustment per the fabricator's rules.
3. Lead time: embedded designs generally cannot run on 1–3 day quick‑turn schedules — expect roughly three extra days over standard.
4. Complete fab notes: layer and orientation of each embedded part, XY coordinates, cavity dimensions and depth tolerances, minimum clearance to cavity walls, and component datasheets. Every missing item is another round of EQ back‑and‑forth.

Closing: embedded passives are a calculated trade, not a party trick

When we help customers evaluate embedded designs, three misjudgements come up most often:

• Embedding everything to save space without checking what 15–20% tolerance does to the circuit
• Placing embedded parts directly under high‑speed traces and creating impedance discontinuities
• Incomplete fab notes that add two weeks of prototype back‑and‑forth

The right use of embedded passives is trading tolerance headroom for space and reliability where the circuit can afford it — not replacing SMT wholesale.

eCloud provides prototyping and DFM pre‑review services from standard multilayer boards through HDI and high‑frequency designs, with hands‑on familiarity with embedded‑passive stackup planning and manufacturing constraints. Evaluating embedded design feasibility? Talk to our engineering team at the layout stage to confirm tolerances, stackup, and fab‑note completeness — before the issues surface at prototyping.