July 26, 2026
When main chips move to 0.4mm pitch and below while the enclosure refuses to grow, traditional through-hole-plus-dog-bone fanout hits a wall: drills too big, pads too close, reference planes shot full of holes. Any-layer HDI (also called ELIC, every-layer interconnect) exists for exactly this bottleneck — laser microvias are allowed between every pair of adjacent layers, so signals can step down through the board like a staircase, right under the component. This article organizes the design workflow, microvia rules, and manufacturing requirements so your first any-layer board doesn't cost you three reroutes.
Conventional multilayer boards mix through‑hole, blind, and buried vias, but mechanical drills are large and consume space on every layer they cross — which devours routing channels fast in dense areas. Any‑layer differs in that L1‑L2, L2‑L3, L3‑L4, and every other adjacent pair permits a laser microvia. Signals no longer detour to find a legal transition point; they drop one layer exactly where needed. Two direct benefits: inner layers are no longer blocked by large via pads, and fine‑pitch parts escape cleanly in place. At its core, any‑layer is a BGA escape technology — it solves the precise moment when routing becomes impossible on a conventional stackup.
Any‑layer's cost comes from process steps, not exotic materials: sequential lamination adds cost and registration risk with every cycle. Run this checklist before committing:
If none apply, a standard 1+N+1 or 2+N+2 HDI stackup is often enough, at far better cost and lead time.
A practical rule: if adding board area or changing a package solves the escape problem, do that first. Any‑layer should be the last item on the list.
Microvias carry one non‑negotiable physical limit: too deep relative to diameter and plating becomes unreliable, producing vias that crack under thermal cycling. The industry rule of thumb holds the depth‑to‑diameter ratio near 1:1 — meaning microvia dimensions are not the designer's guess but a function of the fabricator's dielectric thickness and laser drilling capability.
For chaining through multiple layers there are two structures:
For a team's first any‑layer board, choose staggered unless the fabricator explicitly endorses stacked and the budget allows.
The most common any‑layer failure mode is designing first and asking the fabricator later. The correct order has three steps:
First, before starting, obtain the fabricator's standard any‑layer stackup: layer count, interlayer dielectric thickness, copper weights, microvia drill and pad capability, and via‑fill/cap support — then build design rules on those numbers.
Second, assign layers with purpose: at least one solid ground layer, dedicated power layers, and only then signal layers. Even with many layers available, don't let every layer become random routing — it destroys return paths and defeats debugging.
Third, map the BGA escape before routing a single trace: which rows stay on top, which drop to L2 via microvia, which nets must stay shortest (clocks, DDR, RF). Skipping this step typically costs three reroutes later.
The standard any‑layer escape pattern is clean: outer row routes on L1; second row takes a microvia in‑pad down to L2; inner rows chain microvias to deeper layers. Traces stay short and no large via pads block the channels.
But in‑pad drilling brings one process issue that must be handled: an open via wicks solder down the barrel during reflow, causing voids or opens. The fix is VIPPO (via‑in‑pad plated over) — drill, plate, fill, and plate over so the pad returns to flat.
Critical reminder: VIPPO must be explicitly called out in fab notes. Never assume it's included; this is a classic source of quote and build discrepancies.
Layer‑change freedom doesn't suspend current physics. High‑speed signals need a solid return path, usually a ground plane; too many antipads or long rows of vias slicing the plane force return currents to detour, raising noise and EMI.
Two easy rules:
Combined with tight via clustering and ground stitching, this avoids the "Swiss cheese plane" — the most common signal‑integrity killer on any‑layer boards.
Any‑layer documentation demands exceed a standard board's. Drill data must clearly distinguish laser microvias from mechanical holes, and filled/capped vias from normal plated ones.
Fab notes should cover at minimum:
Common failure patterns:
| Failure mode | Root cause | Countermeasure | | :--- | :--- | :--- | | Microvia cracking | Aggressive stacked structures, aspect‑ratio violations | Follow fabricator limits; prefer staggered | | Misregistration | Insufficient annular rings, aggressive minimum chasing | Use adequate annular rings; don't chase minimums without cause |
Before releasing Gerbers, run the checklist: stackup confirmed, via sizes confirmed, VIPPO noted, planes unbroken, ground vias at layer transitions, DRC clean.
Any‑layer hands designers layer‑change freedom, priced in costlier processes, longer lead times, and stricter manufacturing rules. Its outcome is roughly 80% decided before work starts: whether the stackup was locked with the fabricator, whether the BGA escape was mapped, whether via structures kept reliability margin.
eCloud provides prototyping and DFM pre‑review from standard HDI through any‑layer builds, with accumulated high‑density design experience across high‑speed networking, edge AI, and mobile‑class products. Evaluating a stackup for a sub‑0.4 mm‑pitch project? Talk to our engineering team before layout begins to get manufacturable stackup parameters and microvia rules — and cut reroute and prototype risk to a minimum.
