August 28, 2026
As AI processors integrate more logic dies and high-bandwidth memory (HBM), the advanced-packaging challenge is shifting from whether heterogeneous integration is possible to whether packages can become larger, interconnects can become shorter, and acceptable cost and yield can still be maintained. CoWoS, CoPoS, and CoWoP may sound similar, but they address different constraints. CoWoS is a 2.5D packaging platform already in volume production. CoPoS explores moving selected processes from circular wafers to rectangular panels. CoWoP goes further by investigating whether an advanced platform PCB can assume some of the functions traditionally handled by a package substrate. For PCB engineers, the key issue is not the acronyms themselves. It is the changing boundary between semiconductor packaging and the system board.
CoWoS stands for Chip‑on‑Wafer‑on‑Substrate. Its central concept is to integrate GPUs, ASICs, chiplets, and HBM through an interposer before connecting the complete structure to a package substrate.
The interposer provides much finer interconnects than a conventional PCB or organic substrate. This shortens die‑to‑die signal paths, increases bandwidth, and can reduce I/O power consumption.
TSMC publicly identifies three main CoWoS architectures:
| Technology | Interposer structure | Main characteristic | | :--- | :--- | :--- | | CoWoS‑S | Silicon interposer | High interconnect density with TSVs and embedded deep‑trench capacitors | | CoWoS‑R | RDL interposer | Polymer and copper structure offering greater scaling flexibility | | CoWoS‑L | RDL plus local silicon interconnects | Uses silicon only in high‑density regions to balance size and local routing density |
According to TSMC, CoWoS‑S supports an interposer of approximately 3.3 reticle sizes, or about 2,700 mm². CoWoS‑L and CoWoS‑R are recommended when the required interposer exceeds that range.
These options should not be reduced to a simple premium, mid‑range, and economy hierarchy. Selection depends on die‑to‑die bandwidth, package size, power integrity, thermomechanical stress, and cost targets.
CoPoS is commonly interpreted as Chip‑on‑Panel‑on‑Substrate. Its purpose is to explore the use of rectangular panels for RDL formation and die integration, potentially improving area utilisation for very large packages.
When large packages are arranged on a 300 mm circular wafer, incomplete units near the wafer edge can reduce usable area. A rectangular panel may provide more efficient placement and allow more packages to be processed in one cycle.
Panelisation, however, involves much more than changing the carrier's shape. Larger formats create challenges involving:
The economics of CoPoS therefore cannot be inferred from area utilisation alone. Equipment investment, process yield, materials, and customer qualification will determine its actual cost.
Public reporting has discussed a 310 × 310 mm starting format and research into larger panels. Actual production dimensions, schedules, and customer programmes should still be confirmed through formal announcements from the relevant technology providers.
CoWoP is generally expanded as Chip‑on‑Wafer‑on‑Platform PCB. The concept under discussion is to remove the conventional package substrate and some BGA interconnect levels, allowing the die‑and‑interposer assembly to connect more directly to an advanced platform PCB.
A conventional path can be simplified as:
Logic/HBM → interposer → package substrate → BGA → system PCB
The proposed CoWoP path attempts to shorten it to:
Logic/HBM → interposer or reconstructed structure → advanced platform PCB
Fewer interconnect levels could shorten signal and power paths while reducing some parasitic inductance and interface loss. The functions of the package substrate would not disappear, however. They would move into the PCB.
This would impose much stricter requirements on the platform PCB:
CoWoP should therefore not be described as replacing an ABF substrate with an ordinary motherboard. It requires PCB technology to move toward packaging‑level interconnect capability.
At the time of writing, CoWoP product adoption, physical implementation, and production schedules are still based largely on industry reports and supply‑chain information. The source article associates the architecture with a specific NVIDIA Rubin device, but no NVIDIA primary source was found to confirm that claim. It should therefore remain classified as unverified.
| Comparison | CoWoS | CoPoS | CoWoP | | :--- | :--- | :--- | :--- | | Main objective | Integrate logic dies and HBM at high density | Improve processing and area efficiency for large packages | Shorten the interconnect path between packaging and the system PCB | | Main carrier | Silicon or RDL interposer plus package substrate | Panel RDL plus package substrate | Interposer/reconstructed structure plus advanced PCB | | Maturity | In volume production with formal technology variants | Development and pilot‑line stage | Concept validation and supply‑chain sampling stage | | Key risks | Interposer size, warpage, thermal management, and cost | Large‑area alignment, warpage, uniformity, and yield | PCB fine features, flatness, reliability, and testing | | PCB impact | Higher demand for high‑speed, high‑layer‑count system boards | Potential convergence with panel materials and equipment | PCB directly assumes selected packaging functions |
These technologies are not necessarily sequential generations, nor must one replace another. Future systems may use different or hybrid architectures depending on bandwidth, package size, power, cooling, and cost requirements.
Whether CoWoP enters production on any specific schedule is important, but the more practical task for PCB suppliers is to prepare for packaging‑level manufacturing requirements.
Project reviews should address:
These requirements interact. Increasing copper thickness to improve current capacity can make fine‑line etching more difficult. Smaller microvias raise interconnect density but place tighter demands on laser drilling, desmear, plating, and reliability. The specifications must therefore be reviewed as a complete system through DFM rather than optimised independently.
CoWoS has demonstrated the value of interposers for integrating large logic devices and HBM. CoPoS explores panel processing as a path beyond wafer‑size and manufacturing‑efficiency limitations. CoWoP takes the question further: if selected packaging functions move into the platform PCB, the PCB may become part of the high‑density integration structure rather than simply a motherboard carrying packaged components.
R&D teams do not need to place every emerging acronym into product specifications immediately. They should, however, monitor fine‑line routing, microvias, large‑board warpage, high‑current delivery, low‑loss materials, and packaging‑level testing requirements.
For AI server, high‑performance computing, or large high‑layer‑count PCB projects, material and DFM reviews should begin before the stackup and layout are finalised. The eCloud engineering team can assist with laminate selection, impedance structures, microvia arrangements, and manufacturing‑risk reviews, helping prevent packaging‑driven requirements from becoming cost or yield problems after prototyping.
