July 1, 2026
As PCIe 7.0 enters mass-production planning and 224G SerDes becomes standard for next-generation AI server switches, Taiwan R&D engineers face more than just higher layer counts or more complex stackups — they confront a physical lower bound. In the PCIe 5.0 era, M7-grade CCL could carry signals 12 to 14 inches; with PCIe 6.0/7.0, picking the wrong substrate means signals may attenuate below the receiver threshold in under 5 inches. M7, M8, M9, and M10 are no longer just CCL marketing tiers — they are hard constraints that must be locked down at design time. This article starts from signal physics, then breaks down the differences between the four grades, the material selection decision matrix, and the 2026 supply landscape for low-Dk CCL.
Signal attenuation in copper traces rises non‑linearly with frequency – a known principle, but the pivotal shift in 2026 is the step change in attenuation rate:
Stackup interconnect distance, midplane trace length, and connector launch design are all retroactively bound by CCL grade. Once you commit to 224G PAM4 on the motherboard, the CCL grade has almost no room for “downgrading to save cost” – the signal simply won't reach the GPU or switch chip.
Read in reverse: the CCL grade you plan to use defines the maximum signal‑link length, which in turn defines the rack's physical layout.
A common misconception is that going from M8 to M10 is “just a resin formula change.” In reality, it requires synchronised generational upgrades to resin, glass cloth, and copper foil – fall short on any one, and the board's high‑frequency performance collapses.
All three must hit spec simultaneously. This explains why M9/M10 yields are naturally lower than M7/M8 – what's being upgraded isn't a formula, it's the entire material ecosystem.
For R&D engineers, the first step is mapping the target signal rate to a CCL grade. The table below summarises M6 through M10:
| CCL Grade | Industry Term | Df @10GHz | Target Bus / Rate | Primary Application | | :--- | :--- | :--- | :--- | :--- | | M6 | Very Low Loss | 0.003–0.005 | PCIe Gen 4 / 25G–56G | General‑purpose servers, 100G/400G switches | | M7 | Ultra Low Loss | 0.002–0.003 | PCIe Gen 5 / 56G–112G | Early AI servers (A100/H100), 400G switches | | M8 | Extreme Low Loss | 0.0015–0.002 | PCIe Gen 6 / 112G PAM4 | Current AI mainstream (NVIDIA Blackwell/GB200), 800G switches | | M9 | Super Extreme Low Loss | 0.0010–0.0015 | PCIe Gen 7 / 224G PAM4 | Next‑gen AI (NVIDIA Rubin), 1.6T switches, optical comm modules | | M10 | Hyper Extreme / PTFE class | <0.0010 | Post‑PCIe Gen 7 / 224G+ | 3.2T switches, silicon photonics (CPO) packaging substrates, high‑frequency radar |
In practice: first lock the signal rate, then derive the CCL grade; from there, the bound glass‑cloth and copper‑foil specs determine yield risk and lead‑time exposure. Discovering an M9 lead‑time uncertainty only after the BOM is finalised usually means reworking the entire project schedule.
M8+ CCL is not a patent‑protected technology, but the upstream materials hit chokepoints simultaneously:
The result: if a spec‑jump exceeds what material vendors can adapt to within a year, the entire BOM stalls. AWS, Google, and NVIDIA typically give CCL vendors under 18 months to bridge the M7‑to‑M10 gap, which is the root cause of the 2026 supply fault line.
For R&D, this means high‑grade CCL selection must align with the fab on material availability 6 to 9 months in advance – not when the layout is nearly complete.
The market once treated high‑grade CCL capacity as exclusive Japanese territory. The H2‑2025 through 2026 Southeast Asia expansion is rewriting that structure:
For R&D engineers, two takeaways: first, Southeast Asian capacity is no longer “low‑end transfer” – M8 and M9 grades are now stably available locally. Second, material selection must factor in logistics and geopolitical considerations: whether your CCL vendor's primary site and your fab's primary site fall within the same supply network directly affects project material flexibility.
The M7‑to‑M10 generational shift is a physical necessity forced by signal physics – once you design for 224G PAM4, the CCL grade is not a choice but a physical floor. For R&D and procurement teams, three things must move forward earlier:
eCloud has built substantial experience in high‑speed PCB (including M7/M8/M9‑grade laminates), multi‑stage HDI stackups, and AI server projects. Planning your next high‑speed project? Reach out to our engineering team for DFM review and material selection guidance at the layout stage – keeping signal integrity and material‑supply risk in check from the start.
