I. The Compute Tray is No Longer "One Board," but a Synergy of Five

In the past, when designing servers, we were accustomed to viewing the entire system as a motherboard plus peripheral accessories. But stepping into the Compute Tray of the Rubin generation, you will find at least five types of PCBs operating synchronously:

• HPM Bianca Motherboard: The core high‑speed board carrying the CPU and GPU.
• Midplane: Replaces the previous Cable Cartridge.
• NVSwitch Board: Responsible for NVLink intra‑rack interconnection.
• CX9 Network Card Board: 800G high‑speed network interface utilising an HDI structure.
• CPX Mezzanine Card: Exclusive for Rubin inference computing, integrating GDDR7.

Every board's layer count, materials, and manufacturing processes are being rewritten. Most crucially: the Midplane is an entirely new PCB category created out of thin air – it completely did not exist in the GB200 and GB300 generations.

II. Why Are Layer Counts Stacking Higher? The Inevitability Forced by Signal Physics

Many people think increasing layer counts is something engineers do “just because they want to.” In reality, this is a strict constraint driven by high‑speed signal physics.

NVLink Speeds Double, Loss Budgets Halve

The signal rate for NVLink 5 is 112G PAM4, upgrading to 224G PAM4 in NVLink 6, and reaching 448G SerDes in Rubin Ultra.

• For every doubling of speed, the signal loss budget must be halved.
• Over the same 30‑centimetre transmission path, a 224G signal will incur nearly double the loss of a 112G signal.
• To maintain signal integrity, reference layers and shielding layers must be added, and microstrip line widths must be increased.

The Clear Trajectory of Layer Evolution

| PCB Type | GB200 | GB300 | Rubin NVL144 | Rubin Ultra | | :--- | :--- | :--- | :--- | :--- | | HPM Motherboard | 22 Layers | 22+OAM | 24 Layers | 26 Layers | | NVSwitch | 24 Layers | 26 Layers | 32 Layers | 40+ Layers | | Midplane | None | None | 44 Layers | 78 Layers | | CX9 HDI Card | None | None | 22 Layers | 24 Layers |

The increase in motherboard layers is relatively mild, but NVSwitch sees a massive jump, and the Midplane goes from zero straight to 78 layers – a magnitude of evolution the PCB industry has not seen in the past decade.

III. The Chasm of CCL Grades: Why is the Leap from M7 to M9 So Difficult?

The “blood” of a PCB is the Copper Clad Laminate (CCL). Panasonic's Megtron series from M4 to M9 is essentially a materials science race involving the dielectric constant (Dk) and dissipation factor (Df):

• M4 (FR‑4): Dk ≈ 4.4, Df ≈ 0.020 – Consumer electronics grade.
• M7: Dk ≈ 3.3, Df ≈ 0.002 – GB200/300 mainstream.
• M8: Dk ≈ 3.1, Df ≈ 0.0012 – Rubin motherboard requirement.
• M9: Dk ≈ 3.0, Df ≈ 0.0007 – Rubin Midplane and CPX requirement.

The difficulty of stepping from M8 to M9 is not about tweaking a formula; it is a simultaneous generational shift across three major materials: the resin system, fibreglass cloth, and copper foil.

• The resin must switch to a hydrocarbon resin paired with modified PPO.
• The fibreglass cloth must utilise 99.9% SiO₂ quartz fibre (Q‑Glass).
• The copper foil must reach HVLP4/5 grades, with surface roughness below 0.6 µm.

If any of these three materials fails to meet the standard, the entire board must be scrapped. Yields plummet from 85% in the M7 generation to about 50% for M9. This is why only three companies globally – Panasonic, Showa Denko, and Isola – can stably mass‑produce M9 CCL.

IV. Fibreglass Cloth: The Invisible Crucial Skeleton in CCL

CCL volume is comprised of about 40% fibreglass cloth, yet it almost entirely dictates the overall Dk performance of the board. The evolutionary logic of the five generations of fibreglass cloth is as follows:

• E‑Glass: Traditional fibreglass, consumer electronics grade.
• NE‑Glass: Low‑Dk generation one, GB200 mainstream.
• NER (Low‑Dk2): GB300/Rubin mainstream, with a global annual capacity of only about 100 tons.
• NEZ (Low‑Dk3): Prepared for the Rubin Ultra Midplane.
• Q‑Glass: Quartz fibre, Rubin Midplane/CPX requirement.

Japan's Nittobo alone commands over 90% of the high‑end fibreglass cloth market share. Prices were already hiked by 20% in August 2025, and the market expects further increases in the first half of 2026. For Taiwanese PCB manufacturers, pricing power for upstream materials is almost entirely in the hands of Japanese companies – a reality they must face when planning high‑end product lines.

V. Copper Foil: A 0.5‑Micron Difference Determines Entry into the Rubin Supply Chain

When discussing why 224G signals must be paired with copper foil of HVLP4 grade or higher, we must return to a fundamental physics concept: the Skin Effect.

• High‑frequency signals concentrate on an extremely thin “skin” on the conductor's surface.
• The skin depth for a 224GHz signal is only about 2 to 3 µm.
• If the copper foil surface has a 3 µm protrusion, the signal must “climb over the mountain.”
• Equivalent resistance increases by 25‑40%, signal attenuation rises by 3 dB/m, and impedance discontinuities cause reflections.

The five‑generation evolution of HVLP copper foil is essentially a challenge against manufacturing limits, grinding surface roughness (Rz) all the way down from 6‑10 µm to 0.3‑0.5 µm:

• HVLP3: Rz 1.5 – 2 µm, GB200/300 mainstream.
• HVLP4: Rz 0.6 – 1 µm, Rubin motherboard requirement.
• HVLP5: Rz 0.3 – 0.5 µm, Rubin Ultra Kyber Midplane requirement.

Global manufacturers capable of mass‑producing HVLP4 are highly concentrated among Japanese (Mitsui, JX, Furukawa, Fukuda) and Korean (ILJIN, LOTTE) companies. Other regions in Asia are still playing catch‑up.

VI. HDI Stages: Yield Nearly Halves with Every Added Stage

HDI designs use “stages” to indicate complexity:

• 1‑Stage: Smartphone grade, yield approx. 95%.
• 3‑Stage: High‑end communications and industrial use, yield approx. 70%.
• 5‑Stage: GB300 OAM and Rubin CX9/CPX requirement, yield approx. 40%.
• 6‑Stage (Anylayer): Rubin Ultra Kyber demand, yield only approx. 25%.

Adding one stage means facing several new hurdles:

• One more round of laser drilling.
• One more lamination cycle, accumulating interlaminar stress.
• Another round of challenges in microvia copper filling and plating uniformity.
• Line widths and spacing are continuously compressed, approaching the physical limits of the SAP (Semi‑Additive Process).

This is why manufacturers capable of producing 32+ layer Ultra‑Low‑Loss PCBs and 5/6‑stage HDIs can be counted on one hand globally.

VII. Midplane: The Biggest Piece of the Pie Created Out of Nowhere in the Rubin Generation

GB200 and GB300 used Cable Cartridges to connect GPUs and switch chips. While theoretically a high‑speed solution, in reality, it became the biggest bottleneck for mass production:

• Thousands of copper cables per Tray required manual soldering, taking over two hours to assemble.
• Flyover Cables occupied significant space, obstructing liquid cooling layouts.
• Physically, 224G signals cannot transmit over long copper cables.
• Fault diagnosis was incredibly difficult, creating a “flying wire hell” for engineers.

Rubin switched to a PCB Midplane to directly solve all these problems:

• Trays can be directly plugged and unplugged, shrinking assembly time from two hours to five minutes.
• A completely cable‑free design pairs perfectly with cable‑free cold plates and liquid cooling layouts.
• Adopting M9 + Q‑Glass + HVLP4 is mandatory to support 224G routing.
• The entire Midplane can be integrated with a BMC for real‑time monitoring.

From the 44‑layer Midplane in the Rubin NVL144 to the 78‑layer rack‑level Midplane in the Rubin Ultra Kyber, this board is rapidly becoming the single category with the highest value proportion in the entire rack's PCB – estimated to account for 38% of the Rubin Ultra rack's total PCB value.

VIII. Observations for PCB Manufacturers and Engineering Teams

The three‑year leap from GB200 to Rubin Ultra is essentially not just a “PCB price hike,” but a forced upgrade of the entire industry chain to aerospace‑grade materials. For the Taiwanese PCB supply chain, there are several key observations worth reviewing repeatedly in engineering and business strategies:

• Material Chokepoints Are Real: M9 CCL, Q‑Glass fibreglass cloth, and HVLP5 copper foil are almost entirely controlled by Japanese companies. Taiwanese manufacturers' pricing power and mass production timelines directly determine whether they can secure high‑end orders.
• Layer and Stage Counts Are the Admission Tickets: 32+ layer Ultra‑Low‑Loss PCBs and 5+ stage HDIs are the hard thresholds for entering the tier‑one AI server supply chain.
• The Midplane is a Once‑in‑a‑Decade New Category: For board manufacturers with experience in high‑layer lamination, this is a rare “out of nowhere” opportunity.
• DFM and Prototyping Capabilities Dictate Customer Retention: As design complexity leaps from 22 layers to 44 and 78 layers, the value of early‑stage DFM (Design for Manufacturability) consulting and rapid prototyping will be vastly amplified.

The AI computing arms race is rewriting the competitive landscape of the PCB industry for the next decade. From signal physics and materials science to manufacturing limits, every variable is redefining what constitutes a “high‑end board.” For all R&D engineers and decision‑makers, understanding the physical roots of these changes is more important than chasing trending buzzwords – because the next wave of order allocations will be officially revealed in the first half of 2026.