1.1 Continuing the Discussion on Manufacturing Processes

Last week, we discussed the applications of V-cut and Mouse Bite in panelization to solve mechanical stress issues. This week, we shift our focus to the more microscopic electrical dimension—Back Drilling.

As the high-speed era of 25Gbps, 56Gbps PAM4, and even 112Gbps arrives, the often-invisible Via Stubs on PCBs have become the number one killer of Signal Integrity (SI). This article will deeply analyze the physical mechanism of back drilling technology, factory processes, layout specifications, and demonstrate how eCloud PCB achieves the ultimate process of controlling stub lengths within 5 mils.

2. Core Technology: The Physics of High-Speed Signals and Via Stubs

2.1 What is a Stub?

In multilayer board design, when a signal transitions from the Top layer to an inner layer (e.g., Layer 3) for transmission, a standard Plated Through-Hole (PTH) passes through the entire board thickness. The section of the "metal tube" from L3 to the Bottom layer that is "not connected to any trace and left floating" is the Via Stub.

2.2 Electrical Hazards of Stubs: Parasitic Capacitance and Resonance

In low-speed circuits, stubs have minimal impact; but in high-speed circuits, a stub acts like a parasitic capacitor and an open transmission line.

1. Parasitic Capacitance Effect: According to the rule of thumb, the parasitic capacitance density of a via stub in FR-4 material is approximately 0.2 pF/100 mil. A 100-mil stub introduces about 0.2 pF of capacitance, causing a sudden drop in impedance on the high-speed signal path, leading to reflections and signal jitter.

2. Quarter-Wave Resonance: This is the most critical effect. When the stub length equals 1/4 of the signal wavelength, the reflected wave cancels out the incident wave due to phase opposition, causing the signal energy at that frequency to be "absorbed," creating a deep dip in the Insertion Loss (S21) curve.

   Resonant Frequency Formula:

   • Case Study: If the substrate Dk=4.0 and the stub length is 100 mil, the resonant frequency is approximately 14.75 GHz.
   • Impact: For a 25Gbps signal (fundamental frequency 12.5GHz), this resonance dip falls right within the signal bandwidth, which can cause complete link failure.

Via stub within a circuit model. There is parasitic capacitance with and around the via and its stub. These parasitics modify the via’s impedance as some function of frequency.

Stub Length vs. Supported Rate Comparison Table:

| Stub Length | Resonant Frequency (approx.) | Applicable Maximum Rate | Key Conclusion | | :--- | :--- | :--- | :--- | | 100 mil | 15 GHz | < 5 Gbps | Not suitable for high speed | | 20 mil | 75 GHz | ~ 25 Gbps | Standard back drilling specification | | 10 mil | 150 GHz | ~ 56 Gbps | Gold standard for 25Gbps+ | | 5 mil | > 250 GHz | 112 Gbps+ | eCloud PCB's Precision Process |

3. Process Principle: How Factories Achieve "Depth-Controlled Drilling"

"Back drilling" uses a slightly larger drill bit than the original via, entering from the backside to precisely cut off the excess copper wall of the stub. This is a process with extremely high requirements for depth control.

3.1 Key Challenge: Depth Control

How to ensure the drill bit cuts the stub without damaging the effective circuit layer just a few mils above?

1. Mechanical Dead Zone Control (Traditional): Relies on the drill machine's Z-axis to set a fixed depth. However, due to PCB thickness tolerances (approx. ±10%) and warpage, this method has significant error and typically requires a 10-15 mil safety margin, failing to meet ultra-high-speed demands.
2. Electrical Contact Sensing (Adopted by eCloud PCB): Uses the weak current signal generated when the drill bit contacts the copper layer as a "zero reference point."
   • Principle: Drill bit descends → senses contact with internal copper layer → sets as depth 0 → drills down a precise set value (e.g., 5 mil) → retracts.
   • Advantage: Without introducing high-end blind/buried vias and multiple lamination cycles, and while balancing cost and yield, electrical contact sensing back drilling is currently the most feasible method in practice for controlling stubs to <5 mil.

3.2 Back Drill Hole Size Design

The back drill hole diameter ((D_{backdrill})) must be larger than the original via diameter ((D_{via})) to allow for alignment tolerance.

• IPC Recommendation: .
• Risk: If the back drill diameter is insufficient, any drilling misalignment can leave thin copper slivers, causing random shorts or antenna effects.

4. Layout Specifications: The Designer's Practical Handbook

During the layout phase, engineers must precisely define back drill rules to avoid production disasters.

4.1 Stack-up Definition and Parameter Setting

In EDA software (Altium/Allegro), it is necessary to define which vias require back drilling (e.g., drilling from Bottom to Layer 3).

Back Drill Size Calculation:

• Oversize Recommended Value: 4-5 mil per side (standard process); 3-4 mil per side (precision process).

4.2 Keep-out Zone: Absolute Defense

This is the most error-prone step. The back drill hole is larger than the original hole, so surrounding traces must be avoided, otherwise they will be drilled through.

Keep-out Diameter Calculation: Example: If Via=10mil, Back Drill Oversize=5mil, Safety Clearance=8mil. Then Keep-out Diameter =

• Note: This Keep-out area must be applied to all layers through which the back drill passes.

4.3 Anti-pad Optimization

Back drilling removes metal, increasing the impedance in the via area. To maintain Zo (Characteristic Impedance) continuity, anti-pad sizes need optimization, and even shrinking the anti-pad on back-drilled layers appropriately to compensate for capacitance loss is recommended. 3D simulation (e.g., HFSS) verification is advised for 25Gbps+ signals.

5. Demonstrating Professionalism: eCloud PCB's Precision Process

In designs for PCIe Gen5 (32GT/s) and 112G PAM4, the traditional IPC Class 2 standard (Stub ~ 10-15 mil) is stretched thin. eCloud PCB, focusing on high-end prototyping and small-batch production, offers solutions that exceed industry standards.

5.1 Challenging the 5mil Limit

• Industry Pain Point: General factories, due to equipment precision limits, require designers to reserve larger stub lengths (safety margin), leading to high-frequency signal attenuation.
• eCloud Advantage: Implements high-end depth-sensing drilling machines and X-Ray real-time alignment systems.
  • Stub Control Capability: Nominal 5 mil (0.127 mm), with stable real-world control between 2~6 mil.
  • Back Drill Alignment Accuracy: ±1 mil, allowing for denser routing.

5.2 Why is 5mil Important?

For 112Gbps PAM4, the signal bandwidth extends to 56GHz.

• 10 mil Stub: Although its resonant point is at 150GHz, its capacitive effect is enough to deteriorate Return Loss (RL) around 40GHz.
• 5 mil Stub: Halves the parasitic capacitance and pushes the resonant point beyond 300GHz. Simulations show this can improve high-frequency insertion loss by 0.3~0.5 dB. In stringent Link Budget calculations, this often determines the Pass or Fail outcome of certification tests.

5.3 Practical Case Study

A server client faced BER (Bit Error Rate) exceeding specifications during PCIe Gen5 testing. Analysis revealed the original manufacturer's back drill stubs averaged 13 mil. After switching to eCloud PCB's 5mil process, Return Loss improved by 3dB, eye diagram opening increased by 15%, and certification was successfully passed.

6. Conclusion

From last week's V-cut to this week's Back Drill, we have witnessed the evolution of PCBs from mechanical support structures to electrical performance enablers.

For high-speed designers, "Zero Stub" is the ultimate goal. Although Blind/Buried Via technology can also solve the problem, considering the trade-offs between cost and process complexity, back drilling will remain the mainstream choice for high-end boards for the next 5-10 years.

Key Takeaways:

1. Physics Level: Stubs are high-frequency killers; back drilling is mandatory for 25Gbps+.
2. Process Level: Specifying "Electrical Contact Sensing" control is key to achieving < 5 mil accuracy.
3. Design Level: Strictly calculate the Keep-out Zone to prevent drilling through inner layer traces.
4. Supply Chain: Choosing a manufacturer with 5mil back drill capability (like eCloud PCB) is the foundation for 112G product success.

We hope this report serves as a practical guide on your desk. If you have more questions about high-speed manufacturing processes, feel free to discuss!