I. Structural Stability is Foundational: Symmetrical Stack-up and Warpage Prevention Design

Before starting routing, ensuring the board's "structural integrity" is stable is the first step in multilayer PCB design. In practice, a multilayer board is recommended to adopt an even-numbered and symmetric stack-up, which is a fundamental principle to ensure mechanical reliability and process stability.

A symmetrical stack-up allows the materials on the top and bottom to bear relatively balanced thermal stress during lamination and reflow processes. If the stack-up is asymmetric, when different materials (especially copper foil and dielectric) generate stress due to differences in the Coefficient of Thermal Expansion (CTE), it is easy to cause board bending and warpage after cooling.

For HDI boards pursuing thinness (board thickness may be only 0.8 mm or even thinner), stack-up symmetry is an uncompromisable design red line. Good symmetrical design can effectively reduce the risk of deformation during production and use, avoiding solder joint failure or high-speed signal quality degradation caused by warpage.

Design Recommendations:

• Prioritize even-numbered, mirror-symmetrical stack-up: The function and material configuration of the top and bottom layers (dielectric thickness, copper thickness, and copper density) should be symmetrical about the board thickness centerline. For example, Top/Bottom as signal layers, L2/L7 as reference layers, L3/L6 as signal layers.
• Copper Balance: In practice, pay attention to whether the copper coverage of mirror layers (e.g., L1/L8, L3/L6) is similar. Use Copper Pour to balance copper amounts.
• Add Balance (Dummy) Layer if necessary: If circuit requirements cause layer asymmetry, add auxiliary layers without traces or ground shielding layers to distribute stress and reduce warpage risk.

II. The Core of SI: Reference Plane Configuration and GND / PWR Optimization

The quality of high-speed signals hinges on whether the return path is complete and has the lowest impedance. In high-speed design, every signal layer should be paired with an adjacent and continuous reference plane (GND or PWR), allowing high-frequency current to return along the shortest, lowest impedance path directly beneath the signal.

2.1 Ground (GND) Layer is the Best Reference Plane

Since the ground layer has stable potential and is usually a large, continuous plane, it is the best reference layer for high-speed signals. Design principles:

• All high-speed signal layers should be placed as close as possible to a GND layer to minimize the return loop area, reducing EMI and crosstalk risk.
• Never allow high-speed signals to cross split power planes or discontinuous reference layers. Once the return path is interrupted, current is forced to detour, causing loop inductance to surge, easily leading to SI and EMI issues.

2.2 Power and Ground Layer Configuration Strategy (Key for PI)

Power Integrity (PI) is closely related to plane configuration.

• GND-PWR Tight Coupling Configuration (Low-impedance PDN): It is recommended that power and ground layers be adjacent, separated by the minimum dielectric thickness, forming in-plane capacitance (planar capacitance). This helps the PDN maintain low impedance at high frequencies, supporting the transient current demands of ICs.

Common 8-Layer Board Configuration Examples:

• High SI / EMI Performance (Biased towards High Speed) L1(S) – L2(GND) – L3(S) – L4(PWR) – L5(GND) – L6(S) – L7(GND) – L8(S) → Multiple GND planes, suitable for high-speed and EMI-sensitive designs.
• High PI / High Power Consumption Configuration L1(S) – L2(GND) – L3(S) – L4(PWR) – L5(PWR) – L6(S) – L7(GND) – L8(S) → L4/L5 form strong planar capacitance, but beware of the split risk when signal layers reference the power plane.

Design Recommendations:

• Configure at least 2 or more complete GND planes.
• For 8-layer boards, a 4S4P (±1) configuration ratio is recommended to balance SI and PI.

III. High-Speed Routing Practice: Microstrip vs. Stripline Selection

In 8-layer HDI, signals are primarily routed on Microstrip and Stripline, requiring selection based on signal sensitivity.

| Characteristic | Microstrip | Stripline | SI Impact & Trade-offs | | :--- | :--- | :--- | :--- | | Location | Outer layers (L1/L8), referencing the adjacent inner plane. | Inner layers (L3/L6), sandwiched between two planes above and below. | | | Shielding/EMI | Poorer (exposed to air). | Excellent (enclosed by dual planes). | Stripline offers superior noise immunity and lower radiation loss at high frequencies. | | Impedance Control | More challenging (affected by air). | Easier to control and stable (fully enclosed structure). | Stripline provides better impedance control, minimizing reflections and losses. | | Manufacturing & Cost | Simpler, lower cost. | More complex, higher cost (requires tight tolerances). | Complex high-speed applications warrant investment in stripline. |

Layout Impact on SI:

1. Prioritize Stripline for Critical High-Speed Signals: For critical high-speed signals like clocks, DDR Data/Strobe, PCIe, or noise-sensitive traces, prioritize burying them in inner layers using a stripline structure. The two reference planes above and below provide optimal shielding, ensuring signal quality and stable characteristic impedance.
2. Proper Reference Setup for Top-layer Routing: Surface microstrip lines must have a continuous ground plane directly beneath as a reference for impedance control. Simultaneously, as microstrip lines are prone to radiating electromagnetic energy outward, minimize the length of high-speed traces on the outer layer, routing long-distance, highly sensitive signals via inner-layer stripline.
3. Impedance Control Practice: Precise control of characteristic impedance Z0 is fundamental to SI. During design, materials and dielectric thickness (H) must be selected, and target impedance values (e.g., 50Ω single-ended or 100Ω differential) provided to the manufacturer. For high-density differential signals, consider a Coplanar Waveguide (CPW) structure, which uses accompanying ground lines (G1 and G2) to further enhance electromagnetic field confinement and shielding, stabilizing impedance.

IV. Practical Challenge: SI / PI Countermeasures for Crossing Split Planes

One of the most troublesome issues in HDI design is high-speed signal lines crossing power plane splits. When a signal crosses a split, the return path is interrupted, causing loop inductance to skyrocket, leading to signal reflection, crosstalk, and severe EMI radiation.

Solutions (Practical Checklist for Engineers):

1. Fundamental Fix: Optimize Power Plane Continuity: Minimize power plane splits from the source, ensuring GND plane continuity.
2. Mitigation: Add Ground Stitching Vias: When a high-speed signal line must cross a split, add one or more ground stitching vias immediately adjacent to the signal via, connecting the GND planes above and below. These ground vias provide the shortest possible "bridge" for the high-frequency return current, successfully stitching the loop.
3. Strategic Placement of Decoupling Capacitors: Strategically place decoupling capacitors in areas where signal lines must cross splits. These capacitors act as low-impedance paths at high frequencies, serving as "bridges" for the AC return current, coupling it from one split plane to another reference plane.
4. Optimize Routing Angle: Ensure signal lines cross the split gap as perpendicularly as possible. Avoid routing signal lines parallel along the split line, minimizing the length and duration of the increased loop inductance.

Summary: Balancing Signal Layers and Plane Integrity

In 8-layer board design, one should not blindly pursue more signal layers at the expense of plane layers. Insufficient plane layers can cause two high-speed signal layers to be directly adjacent (increasing crosstalk) or increase the Power Delivery Network (PDN) impedance (worsening PI).

The 4S4P configuration (e.g., 4 signal layers paired with 4 plane layers) is the optimal balance point for high-speed applications, considering both SI performance (sufficient reference layers) and PI performance (sufficient planar capacitance). If the high-speed signal count is extremely high and an 8-layer board struggles to meet routing and PI needs, it's better to consider upgrading to a 10-layer board or utilizing HDI's blind/buried via technology rather than compressing the number of plane layers.

Conclusion

The success of an 8-layer HDI stack-up stems from the balanced design of SI, PI, and DFM (Design for Manufacturability). Starting with symmetrical stack-up, rationally configuring GND/PWR layers, and burying critical signals in stripline will allow you to navigate high-speed design more confidently and lay a solid foundation for product reliability.

Best wishes for smooth designing to all engineering partners!