February 25, 2026
This report adopts a problem-solving approach to deeply analyze the underlying physical mechanisms behind the two dominant customer complaints in SMT factories—“monolithing” and “voiding”—and provides practical parameters for RD teams to avoid pitfalls during the layout stage.
In the final mile of electronic product development, the last thing an R&D engineer (RD) wants is a call from the assembly house (EMS). The calls usually go something like this: "Ben, the tombstoning rate on this batch of boards is too high; half of the 0201 components have popped off!" "We ran it through X-Ray, and the center of the BGA is full of voids. We can't ship this batch."
Many RDs instinctively think this is due to poor solder paste printing on the production line or incorrect reflow oven temperature profiles. However, according to statistics from SMT assembly houses, over 70% of soldering quality problems have their roots buried the moment the RD draws the first trace and defines the first pad. This is the so-called DFM (Design for Manufacturability) deficiency.
Tombstoning, also known in the industry as the "Manhattan effect," simply describes a chip component (resistor, capacitor) during reflow where one end is lifted by solder surface tension, standing vertically on the circuit board like a tombstone.
This isn't magic; it's a simple problem of torque balance. When the solder paste melts, the component ends are subjected to Wetting Force. If the forces on both ends are equal, the component self-centers; but if the forces are unbalanced, the stronger side creates an upward torque.
According to the mechanical model, the key indicator for tombstoning is the "Balance Factor" $E_b$: $$ E_b = \frac{T_{driving}}{T_{resisting}} $$
RD's Pain Point: As components miniaturize (e.g., 0201, 01005), the component weight $M$ approaches zero, meaning $T_{resisting}$ becomes very weak. At this point, if the temperature difference between the two pads exceeds 5°C, causing one side's solder to melt before the other, the component will be pulled into a "tombstone" in milliseconds.
If you find a particular component constantly tombstoning, first check if your Layout has made these errors:
Thin Trace on One Side, Copper Pour on the Other (The Worst Practice): This is the most common mistake RDs make. One pad connects via a 4 mil trace, while the other connects directly to a large Ground Plane. The copper pour side acts like a massive heat sink, drawing away heat and causing that side to heat up slowly. When the thin trace side has already reached its melting point (217°C) and starts pulling, the copper pour side is still solid—the component will inevitably flip.
Asymmetric Solder Mask Openings: If one pad is partially covered by Solder Mask while the other is fully exposed (mixing NSMD and SMD), this results in inconsistent areas participating in soldering, leading to unbalanced surface tension vectors.
Component Placement Direction (Shadow Effect): If a small chip component is placed very close to a large inductor or heat sink, the large component can block convective heat from the reflow oven (shadow effect), causing a temperature difference across the small component.
Voids are the most troublesome defect in BGA soldering. They hide inside the solder balls, invisible to Visual Inspection (VI), and only revealed by X-Ray.
When the assembly house complains, RDs must understand the specifications. According to IPC standards, BGA voiding is judged as follows:
| Acceptance Criteria | Class 1 (Consumer) | Class 2 (Bus./Ind.) | Class 3 (Mil./Medical) | Industry Rec. (2012 Update) | | :--- | :--- | :--- | :--- | :--- | | Void Area (Area %) | ≤ 36% | ≤ 20.25% | ≤ 9% | ≤ 6.25% | | Void Diameter (Dia %) | ≤ 60% | ≤ 42% | ≤ 30% | ≤ 25% |
Data Source: Compiled from IPC-7095B specification table.
Warning: Although the specification says 25% is the limit, if voids appear at the "Interface" (Interface Voids), meaning the junction between the solder ball and the package or PCB, even an area of only 5% can significantly shorten fatigue life, causing fractures during Drop Tests.
When RDs place vias directly in BGA pads to save space but fail to treat them with "Plated Fill," disaster is imminent.
RD's Decision Recommendations:
When defining BGA pads, you face this question: Should you use Solder Mask Defined (SMD) or Non-Solder Mask Defined (NSMD)?
Ben's Director-Level Recommendation List:
Many high-end boards (e.g., PCIe Gen5 servers) experience fractures in Top-side BGA solder joints during the second reflow pass (e.g., when assembling the Bottom side). This is the hidden "Piston Effect."
When your BGA footprint mixes VIPPO pads (supported by a copper pillar) with Dog-bone pads (supported solely by resin), the difference in physical properties causes conflict:
As the resin expands violently upwards, it acts like a piston, lifting the Dog-bone region, while the VIPPO region is "nailed" in place. The displacement difference between these two areas generates immense tensile stress, literally tearing apart the already-formed IMC interface at the VIPPO location (Hot Tear).
Finally, let's discuss the QFN bottom Thermal Pad, a common source of RD anxiety. If you use a "full opening" stencil aperture, you are guaranteed to face complaints about large voids and "component floating."
A large area of molten solder paste generates significant surface tension, which can lift the lightweight QFN (Floating), leading to open solder joints on the peripheral leads. Simultaneously, gases trapped under the large expanse of solder cannot escape, forming voids.
Instead of dealing with complaints right before product launch, it's better to uphold quality red lines during the Layout phase. Here is an RD checklist targeting the two kings of SMT assembly complaints:
eCloud Technology specializes in accelerating high-end PCB development. We not only provide advanced processes like LDI laser direct imaging and VIPPO but also utilize data-driven DFM pre-reviews to help RDs identify and eliminate design risks related to tombstoning and voiding right from the start.
"In extreme manufacturing processes, only extreme precision can achieve reliable quality." Every small optimization RDs make during Layout is a giant step for the company in saving millions in rework costs.
