Essential R&D Knowledge: Three Key Decisions in HDI Stackup Design — Don't Let Wrong Choices Eat Up Your Yield and Cost

HDI PCB Stackup Design: Three Key Decisions and Practical Advice

Decision 1: When Should You Decisively Adopt HDI?

Many people rely on experience to guess, but there are actually very clear indicators.

Look directly at the main IC's BGA pitch:

• Pitch ≥ 0.65 mm → A standard board + dog‑bone fanout can usually solve it.
• Pitch ≤ 0.50 mm → Almost certainly requires via‑in‑pad or stacked microvias; HDI is a mandatory choice.
• 0.65 – 0.80 mm → A gray area; you must evaluate the I/O count and routing density.

Next, look at the BGA breakout layer requirements:

• ≤ 4 signal layers → A standard stackup can handle it.
• ≥ 5 signal layers → An HDI stackup is almost the only solution.

Ironclad rule: As long as the design requires microvia‑based via‑in‑pad, regardless of your net count or how fast the speeds are, HDI is a necessary choice – no exceptions.

Stop using “the speed isn’t that fast” as an excuse to reject HDI. The true anchors for this decision are always the package pitch and breakout density.

Decision 2: Which Language Should You Use When Talking to the Fab?

This is something many R&D engineers misunderstand. HDI stackups have two parallel classification systems, and you must know how to use both.

IPC‑2226 Type Classification (For Specification Documents)

• Type I: Core + single‑layer microvia + PTH (entry‑level, common in consumer electronics)
• Type II: Type I + buried vias (medium‑density applications)
• Type III: Core + two or more layers of sequentially stacked microvias (mainstream for smartphones, 5G, and AI modules)
• Type IV – VI: Coreless or every‑layer interconnect structures (ELIC / Any‑layer HDI), applicable to high‑density applications like IC substrates

i+N+i Notation (For Fab Inquiries & Quoting)

• 2+8+2 = 2 build‑up layers on top/bottom + 8‑layer central core → 12 layers total
• 1+b6+1 = 6‑layer core including buried vias + 1 build‑up layer on top/bottom

Practical application guide:

| Scenario | Which system to use | | :--- | :--- | | Writing spec sheets, handling compliance documents | IPC‑2226 Type classification | | Getting quotes from fabs, comparing stackup costs | i+N+i notation |

If you cannot seamlessly switch between these two languages, your communication efficiency with the fab will drop by half.

Decision 3: How to Avoid “Over‑Design” and Wasting Costs?

The most common engineering disaster in HDI stackups isn’t under‑design – it’s over‑design. Every additional sequential lamination cycle adds yield risks and costs.

Four checkpoints for the “Minimum Viable Stackup”

1. Match signal and plane layers – prioritise symmetry

• High‑speed signal layers must be closely adjacent to continuous GND planes.
• Pair Power and GND to lower PDN impedance.
• Keep the number of signal and plane layers even, arranged symmetrically around the centreline.
• Dielectric and copper thickness on both sides must be balanced, otherwise warpage will find you.

2. Via strategy dictates everything

The rule isn’t “use stacked microvias whenever possible”. The priority should be:

• If it can be solved with staggered vias → absolutely do not use stacked.
• If you can use skip vias → avoid multiple laminations.
• Only upgrade to ELIC‑level structures when truly necessary.

3. Match materials to frequency bands – don’t over‑spec

• General high‑speed digital: stable Dk < 3.5, Df < 0.02 is sufficient.
• RF / high‑frequency: consider low‑roughness ED copper foils like Megtron 6.
• Lead‑free reflow processes: Tg must be above 170 °C; standard FR4 is not enough.
• Designs sensitive to the fibre weave effect: choose dense weave styles like 1078, 3313, or 1067.

4. You must account for prepreg tolerances

Prepreg thickness tolerances are usually ±10–15%. Factor this variation into your impedance calculations – don’t just force a single, rigid value.

Three Practical Tips for R&D Teams

First: Move the HDI decision forward to the system architecture phase

Waiting until the Layout phase to go back and revise the stackup will double your costs. Evaluate HDI needs simultaneously while selecting ICs.

Second: Bring the fab into the discussion early

The manufacturability of the i+N+i structure, microvia aspect ratios, and the fab’s material library support are all key to stackup success. Align on these before the Schematic is even completed.

Third: If 2+N+2 works, don’t force a 3+N+3

Over‑design won’t make your board more reliable; it will only increase BOM costs and extend prototyping lead times. Achieving design goals with the simplest architecture is what engineers should always strive for.

Conclusion: Stackup Decisions Are Engineering Judgments, Not Just Technical Issues

There is no universal solution for HDI stackup design. The entire process is a trade‑off across five dimensions: routing density, signal integrity, PDN performance, fab capabilities, and cost.

As long as you internalise the three key decisions above into your SOP, you can avoid 80% of stackup mistakes.

If your project is currently facing challenges with fine‑pitch BGA breakouts, HDI stackup selection, or impedance simulation verification, it is highly recommended to connect with an integrated service provider equipped with HDI engineering capabilities before prototyping. Addressing engineering risks upfront will make the path from prototype to mass production significantly smoother.