Explore the latest trends in PCB design and manufacturing
Explore the latest trends in PCB design and manufacturing
At 1:00 AM, the PM group chat pings with a client's LINE message: "Mass production starts next month, the unit price needs to drop by another 8 cents, or the order might shift to Vietnam." The first ones woken up for a meeting are always Procurement and the Assembly Plant PMs. When the call connects, the assembly plant contact is polite, but the answer is almost always the same: "The design is locked in; I really can't squeeze out any more on my end." This script plays out in every hardware company multiple times a year. The problem is—the play was cast wrong from the very beginning.
Many R&D engineers have encountered this situation: the schematic is fine, the ICs have been verified, and the firmware runs, but the board just won’t connect. After switching to a new batch of components and making another prototype, it mysteriously starts working again. The problem often lies not in the components, but in those seemingly ordinary copper traces. When signal edge rates fall below 1 ns or the operating frequency exceeds 100 MHz, the traces on the PCB are no longer simply “wires,” but transmission lines. The biggest enemy of transmission lines is discontinuity in characteristic impedance.
This article analyses the transition zone—the most vulnerable area in Rigid-Flex designs—and outlines four critical design pitfalls that RDs must avoid.
COMPUTEX 2026 has just concluded, and the figures Jensen Huang dropped while unveiling the Vera Rubin platform at GTC Taipei shocked the entire industry: a single architecture utilizing nearly 2 million components, over 150 Taiwanese supply chain partners, and a 10x improvement in inference performance per watt. However, hidden behind these glamorous numbers is a crisis in packaging substrates for AI servers.
In the high-end electronics industry—whether for automotive, servers, AI accelerator cards, or IoT modules—the demand for HDI (High Density Interconnect) boards climbs every year. However, many R&D engineers share a similar experience: the layout looks beautiful in the EDA tool, DRC passes with flying colors, but the moment it is sent to the fab, the CAM engineer replies with, "This structure will be an epic fail for mass production yield." The problem usually isn't about "whether it can be made," but "whether it can be made consistently." HDI's fine traces, microvias, and thin dielectrics compress process tolerances to their absolute limits. A 0.05 mm oversight could mean an entire batch of boards goes straight to the scrap bin. This is why DFM (Design for Manufacturing) for HDI boards isn't just a recommendation; it is a mandatory course. This article summarizes the most common pitfalls in HDI design to help engineers mitigate risks before sending out samples.
Whenever you're mapping out the stackup for a new project, do you often get stuck on these questions? ●"Does this BGA really need HDI?" ●"The fab replied with 2+N+2, is that the same as IPC Type III?" ●"The client wants to cut costs, but engineers are worried about signal integrity—should we add more layers?" These aren't technical problems; they are decision-making problems. This article cuts straight to the chase, helping you clarify the three key decisions of HDI stackup design in under 3 minutes.
